library verilog;
use verilog.vl_types.all;
entity Memory is
    port(
        Memory_Write_Enable: in     vl_logic;
        Memory_Address  : in     vl_logic_vector(4 downto 1);
        Memory_Write_Data: in     vl_logic_vector(48 downto 1);
        Memory_Read_Data: out    vl_logic_vector(48 downto 1);
        clk             : in     vl_logic
    );
end Memory;
